1. Field of the Invention
The present invention relates to a method of manufacturing an integrated edge structure for high voltage semiconductor devices, and to the related integrated edge structure.
2. Discussion of the Related Art
High voltage semiconductor devices, for example MOS-gated power devices, include PN junctions which must withstand high reverse voltage. Most of PN junctions fabricated by planar technology essentially consist of a first semiconductor region of a given conductivity type diffused into a second semiconductor region of opposite conductivity type.
A depletion region is associated with the PN junction, which can be considered as made up of two regions, a first one along the plane portion of the junction, a second one at the edges of said plane portion. The electric field has a different behavior in the two regions. In the plane portion the equipotential lines are parallel to the junction, the maximum electric field is located at the junction and the breakdown occurs when it reaches the critical value E.sub.CR. At the junction edges, because of the finite junction depth, the equipotential lines are curved, and spaced closer together than in the plane portion. As a consequence, the electric field increases, higher electric fields are associated with smaller curvature radii, i.e. a shallower junction. The breakdown voltage of a PN diffused junction is usually lower than that of the corresponding plane junction, since the electric field in the edge region is much higher. The ratio between the breakdown voltage of the edge and the plane portion is thus below unity.
Several techniques have been developed to increase the ratio, essentially by changing the size of the depletion layer to avoid local increases in the electric field which can lead to early breakdown.
For example GB-A-2163597 describes a technique wherein one or more high resistivity rings are provided around the lateral edges of the junction; in this way the depletion layer spreads over wider regions, so that the spatial charge distribution is widened and the electric field is consequently reduced. The rings are formed by implantation and diffusion of dopants; by controlling the implanted dose and the diffusion process, it is possible to achieve the desired resistivity. Two or more concentric rings, with increasing resistivity from the inner to the outer one, are necessary when the device must withstand high reverse voltages. However, peaks in the electric field value are observed at the interface between two rings, and at the edge of the outer ring. An increase in the number of rings leads to larger spreading of the depletion layer, and the peaks in the electric field are lowered.
Other techniques used for reducing the electric field include rings with high junction depth, floating rings and so on.
In view of the state of the art described, it is an object of the present invention to provide a method of manufacturing an integrated edge structure for high voltage semiconductor devices.